1. Field of the Invention
The present invention relates generally to memory circuits in integrated circuits. More particularly, the present invention relates to systems and methods for improving dynamic random access memory (DRAM) by employing a variable array architecture.
2. Background
The semiconductor industry continues to be driven by the benefits imparted by miniaturization of integrated circuits that comprise commercial devices such as memory chips, controllers, and microprocessors. The ability to fabricate increasingly smaller devices and circuits affords the possibility of greater speed, higher device density, and cheaper cost for a given performance. However, these benefits may incur the potential cost of higher power consumption within a chip, as well as inefficient utilization of the full chip resources. In memory devices, both enhanced memory capacity and speed are desirable in order to increase overall system performance. In dynamic random access memory (DRAM) data is accessed and stored in rectangular or square arrays of memory “cells.” Miniaturization has increased both the density and speed at which DRAM arrays operate, often at the expense of increased power consumption.
In prior art memory systems based on DRAM arrays, a typical memory consists of a group of memory arrays designed so that each array contains similar structure and function. The group of arrays may reside entirely on the same silicon chip, or be distributed on different silicon chips. FIGS. 1(a) and 1(b) illustrate a conventional memory system 2, comprising a plurality of memory arrays 4. Each memory array contains cells arranged in rows and columns so that each cell within an array has a unique address corresponding to the row and column that it occupies. A cell 5 is activated for reading by sending a signal along the address bus (not shown) to access a particular cell to be read. The cell data is output on memory data bus 8, which may be, for example, eight bits wide. When a byte of information is stored in system 2, a single bit 20 of the byte is stored in each of the eight arrays. Optionally, as is well known, two or more bits may be stored in each of the eight arrays to increase the bandwidth. The row and column address of the bit location within each array is the same. When a processor (not shown) requests the information contained in data byte 22, the data is read out by retrieving a plurality of bits 20, one from each array 4, as shown in FIG. 1(a). The data is then output along data bus 8 as byte 22, as illustrated in FIG. 1(b).
In the above example, each array within the system performs in an identical fashion to the other arrays. Control of the overall memory performance is determined in large part by the array design and operating voltage. The refresh rate and power consumption may be reduced by reducing the amount of rows in the array. However, for the same array size, this requires longer wordlines, which requires more cells to be activated during a read or write operation, since all of the cells in a given row must be accessed during such operations. This, in turn, leads to a longer latency period when a row is being activated. The operation speed of the memory system may be increased by increasing the supply voltage, but this results in greater power consumption. Thus, in conventional memory architecture, improvement of one memory feature often results in an adverse impact on another feature.
In light of the foregoing discussion, it will be appreciated that there exists a need to overcome the tradeoffs in power, performance, and speed that are inherent in prior art memory architecture.